1. Field of the Invention
The present invention relates generally to nanowire complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device structures and methods for fabricating these device structures. More specifically, the present invention relates to semiconductor nanowire FET device structures having the suspension height of the nanowire channels altered in order to tune the gate lengths of the resulting nanowire FET device structures.
2. Description of Related Art
This section is intended to provide a context to the invention that is recited in the claims. The description herein may include concepts that can be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
As microelectronic scaling proceeds beyond the 14 nm technology node, the number of levels requiring sublithographic pitches continues to grow. Even with advanced lithographic techniques, such as extreme UV (EUV) or electron-beam lithography (e-beam), certain critical levels, such as fins (for FinFETs or trigates), gates, and dense wiring levels, are expected to demand feature pitches at or below the limits of resolution of direct lithography. Existing patterning solutions in these cases include pitch multiplication techniques such as interleaved multiple exposures, sidewall image transfer (SIT), and directed self-assembly (DSA).
When direct lithography is pushed to its 2-dimensional resolution limit or when pitch multiplication techniques are used, gratings of uniformly sized lines quickly become the easiest pattern to achieve. Deviations from a uniform grating cause poor printing or degrade the achievable pitch. In particular, the ability to pattern lines of different widths becomes difficult at very tight pitches.
The gate level has historically been one of the densest features of a technology and the gate level is expected to reside at or below the limits of lithography as scaling continues beyond the 14 nm node. The ability to modulate gate length, however, has been a powerful design tool for many CMOS technologies. Shorter gate length devices provide enhanced on-current at the expense of greater leakage, while longer gate length devices are slower in the on-state, but consume less power in the off-state. Therefore, a method to modulate gate length without actually printing differently sized gate lines would be of great use in future technology nodes.
A nanowire transistor device structure is characterized by a semiconductor nanowire passing through a gate structure to connect a source region and a drain region. Doing so forms a nanowire channel electrically connecting the source and drain regions such that the gate controls the current in the channel. A nanowire channel FET can be created such that the gate fully surrounds the nanowire such that the channel forms at the surface of the nanowires within the gate. In larger devices, different gate-lengths can be achieved by directly patterning differently sized lines. However, as devices become smaller and smaller, requiring the fabrication of even tinier transistors, it becomes extremely difficult to engineer the various multiple gate lengths.
Therefore, methods for achieving multiple gate lengths at tight gate pitches, as well as the resulting devices, that do not increase production costs are highly desired.